With the trend toward more highly integrated, multi-layer semiconductor devices, the use of multi-layered wiring techniques has been proposed as one of the important techniques for implementing such highly integrated, multi-layer semiconductor devices. Multi-layer wiring techniques typically use metal wire layers and insulation layers that are alternately formed on a top surface of a semiconductor substrate on which circuit devices are formed. In addition, such multi-layer wiring techniques utilize a circuit operation that is performed by electrically connecting the metal wire layers, which are separated by the insulation layers, through via holes.
However, in such a multi-layered metal wire structure the space between the metal wires narrows as the level of integration of the semiconductor device increases. As a result, the effects of parasite resistance or parasite capacitance between adjacent metal wires in the same layer or between lower and upper metal wire layers becomes more significant.
As is known, parasitic resistance or capacitance deteriorates an electrical characteristic due to a delay induced by an RC (resistance and capacitance), disturbs or limits the high speed operation of the semiconductor device, and typically increases power consumption and signal leakage of the semiconductor device.
Accordingly, to reduce the parasitic capacitance, studies for materials having a low dielectric constant K, for example, a SiC family among oxide materials of an existing TEOS (tetra ethyl ortho silicate) family has been progressed actively. However, in the case that new materials with such a low dielectric constant are used, additional equipment must be used and a process parameter optimization of each unit process for the new materials, thereby increasing processing costs.
Accordingly, methods of reducing the parasitic capacitance while using the oxide materials of the existing TEOS family as they are have been studied. As a result, there have been proposed methods where air gaps are formed in an interlayer insulation film between adjacent metal wires in order to reduce an overall capacitance, the so called “air gap formation method at intralevel.” Techniques related to this are disclosed in U.S. Pat. Nos. 6,472,719, 6,423,630, 6,403,461, 6,376,330, 6,358,845, and 6,268,276.
FIG. 1 is a sectional view of a multi-layered metal wire structure where air gaps are formed at an intralevel using a known technique. As shown in FIG. 1, lower metal wire layers 102 are formed on a structure of a semiconductor substrate, upper metal wire layers 106 are formed above the lower metal wire layers 102 via an interlayer insulation film 104, and the upper and lower metal wire layers 106 and 102 are electrically connected to each other through via holes 108. In addition, air gaps 110 are formed in the interlayer insulation film 104 between the lower metal wire layers 102.
However, conventionally, as shown in FIG. 1, the air gaps 110 are formed in only intralevels between the lower metal wire layers 102. That is, because it is impossible to form the air gaps between the lower metal wire layers 102 and the upper metal wire layers 106, there is a limit on the reduction of an overall capacitance.
Accordingly, if air gaps can be formed between the lower metal wire layers 102 and the upper metal wire layers 106, the overall capacitance can be significantly reduced. As a result, there is a strong need for the formation of air gaps at such an interlevel.